Introduction to Verilog: Modules, Number Representations & Comments | Free DV Course|All about VLSI
40:37
Introduction to Verilog: Modules, Number Representations & Comm…
42.4K views7 months ago
YouTubeALL ABOUT VLSI
Mastering Verilog in 1 Hour 🚀: A Complete Guide to Key Concepts | Beginners to Advanced
1:08:06
Mastering Verilog in 1 Hour 🚀: A Complete Guide to Key Concepts …
65.1K viewsMar 9, 2025
YouTubeExplore VLSI
Verilog Basics - STRUCTURE of a Verilog Module | Starting out in Hardware Description Language (HDL)
10:01
Verilog Basics - STRUCTURE of a Verilog Module | Starting out in Ha…
8.3K viewsMay 5, 2020
YouTubeVisual Electric
Lecture 5: Introduction to Verilog
34:19
Lecture 5: Introduction to Verilog
1.4K views2 months ago
YouTubeIIT Roorkee July 2018
Modules - Verilog Fundamentals
21:22
Modules - Verilog Fundamentals
467 viewsMar 3, 2023
YouTubeMetaphysics Computing
What is a Verilog Module | Input & Output Explained | First RTL Code | Chapter 2
14:31
What is a Verilog Module | Input & Output Explained | First RTL Cod…
55 views2 months ago
YouTubeSilicon Simplified
Using Multiple Modules in Verilog
14:20
Using Multiple Modules in Verilog
33.8K viewsMar 24, 2020
YouTubeDerek Johnston
16:35
Find in video from 03:11Using Parameters in Verilog Modules
Introduction to FPGA Part 6 - Verilog Modules and Parameters | Digi-Ke…
27.3K viewsDec 13, 2021
YouTubeDigiKey
16:04
#6 Module and port declaration in verilog | verilog programming basi…
26.5K viewsJun 18, 2020
YouTubeComponent Byte
23:07
Day 1: Introduction to Verilog & Modules | 60-Day Verilog Worksho…
2.5K viewsDec 19, 2024
YouTubeALL ABOUT VLSI
38:50
Lecture 07: Modelling of Digital Circuits
1K views2 months ago
YouTubeIIT Roorkee July 2018
3:25
Find in video from 00:16Using Half Adders as Single Modules
FPGA Programming with Verilog: Module Instantiation
3.1K viewsNov 29, 2021
YouTubedrselim
48:59
Introduction to Verilog | Basics of HDL for VLSI & Digital Design
341 views3 months ago
YouTubeVLSI Simplified
46:45
Port Connection Rules in Verilog | Connect by Order vs Connect by …
10.8K views7 months ago
YouTubeALL ABOUT VLSI
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adder…
575 views1 month ago
YouTubeSly Fox electronics
12:24
Modules and Instantiation in Verilog | #3 | Verilog in English
74.7K viewsJun 28, 2021
YouTubeVLSI POINT
8:11
Mastering Verilog: Modules, Ports & Data Types (Wire, Reg, Logic) | Pa…
40 views6 months ago
YouTubeCrack the Electronics with Rajesh
12:06
UART Transmitter Module in Verilog | Step-by-Step Code Development …
7.7K views7 months ago
YouTubeALL ABOUT VLSI
24:11
Find in video from 07:00Modules and Ports
Introduction to Verilog Part 1
154.4K viewsSep 6, 2014
YouTubePeter Mathys
26:53
Universal Counter in Verilog | Mod, Even, Up Down Counter in One Mo…
1.5K views5 months ago
YouTubeALL ABOUT VLSI
40:43
FIFO Design in Verilog | Handling Different Read/Write Speeds | Prac…
3.4K views4 months ago
YouTubeALL ABOUT VLSI
33:32
Verilog Parameters Explained with PWM Example | 100 Days of FPGA
152 views2 months ago
YouTubeThe Hardware Developer
2:53
Verilog Day-9 | Parameters & Parameterization Explained | RTL …
109 views3 months ago
YouTubeChip Logic Studio
2:53
Verilog Day-9 | Parameters & Parameterization Explained | RTL …
267 views3 months ago
YouTubeChip Logic Studio
3:20
Intel Quartus: Connecting Modules in Verilog
31.5K viewsAug 29, 2018
YouTubeJay Brockman
48:27
Hardware Modeling: Introduction to Verilog-II
19.1K viewsMar 19, 2025
YouTubeNPTEL-NOC IITM
22:02
How to instantiate a Verilog Module, part 1
5.5K viewsJun 19, 2021
YouTubeDigital Logic Design
5:19
1-Verilog Module Component
528 viewsNov 5, 2023
YouTubeShailendra Kumar Tiwari
1:02:42
HDL Bits Complete Guide: Part 03 || Modules: Hierarchy || Verilog Ste…
171 views6 months ago
YouTubeFluxray Electronics
39:34
Arrays and Port Rule Connections in Verilog/SystemVerilog | RTL Desig…
27 views2 months ago
YouTubeVLSI Simplified
See more videos
Static thumbnail place holder

Short videos

0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Desi…
575 views1 month ago
YouTubeSly Fox electronics
2:41
conditional statements in verilog | if else & case
169 views2 months ago
YouTubeChip Logic Studio
2:53
Verilog Day-9 | Parameters & Parameterization Explaine…
109 views3 months ago
YouTubeChip Logic Studio
2:57
Verilog Counter Code with Testbench & Simulation | C…
151 views3 weeks ago
YouTubeChip Logic Studio
2:05
Recover Gold from Computer RAMs
3M views3 weeks ago
TikTokgoldhuntextra
2:56
Verilog Day 11: : Arrays in Verilog
75 views2 months ago
YouTubeChip Logic Studio
2:59
Verilog Day 1: Introduction and Data Types Explained f…
86 views5 months ago
YouTubeChip Logic Studio
2:53
Verilog Day-9 | Parameters & Parameterization Explaine…
267 views3 months ago
YouTubeChip Logic Studio
2:59
Verilog Day 1: Introduction and Data Types Explained f…
69 views5 months ago
YouTubeChip Logic Studio
1:11
How our CPUs actually work! Learn to build one using ve…
205 views5 months ago
YouTubeDropMinted | Electronics
0:16
VerilogVHDL#vlsi#Verilog #VHDL #VLSI #FPGA #Digit…
42 views4 weeks ago
YouTubeVLSI DESIGN LAB
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modelin…
1.5K views2 weeks ago
YouTubeChip Logic Studio
2:56
Verilog Day 6: Testbench in Verilog
64 views4 months ago
YouTubeChip Logic Studio
2:50
Decoder in Verilog HDL with Testbench | RTL Simulatio…
19 views1 month ago
YouTubeChip Logic Studio
2:54
Verilog Day 6: Testbench in Verilog
86 views4 months ago
YouTubeChip Logic Studio
2:52
Decoder in Verilog HDL with Testbench | RTL Simulatio…
117 views1 month ago
YouTubeChip Logic Studio
2:54
verilog mux design | practical rtl coding for interviews
54 views1 month ago
YouTubeChip Logic Studio
3:00
verilog mux design | practical rtl coding for interviews
46 views2 months ago
YouTubeChip Logic Studio
2:59
Verilog Day 5: Loops & Assign Block Explained
122 views4 months ago
YouTubeChip Logic Studio
2:59
verilog mux design | practical rtl coding for interviews
50 views2 months ago
YouTubeChip Logic Studio
Static thumbnail place holder