EDN

Synopsys Donates SystemVerilog Assertion Checkers to Accellera

SAN FRANCISCO — EDA giant Synopsys Inc. has donated a library of advanced SystemVerilog assertion checkers defined in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog to ...
EDN

Introduction to Accellera’s assertion efforts

While verification of complex systems-on-chip (SoCs) poses an unprecedented challenge, a number of factors lead EDA industry leaders to believe that assertion-based verification will likely be the ...
Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
Business Wire

Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem; Third-Party Verification IP Qualified with Questa

Using Questa's native implementation of SystemVerilog, we were able to deploy a very sophisticated coverage-driven, constrained-random verification environment that fully utilized the advanced ...