FriendlyELEC has launched the "Plus" variant of the NanoPC-T6 Rockchip RK3588 SBC using up to 32GB LPDDR5, instead of LPDDR4x RAM ...

In early January 2026, Valens Semiconductor announced a new design win for its VA7000 MIPI A-PHY-compliant chipsets with a ...

Microchip Technology Inc. has claimed the first single-core microprocessor with a MIPI CSI-2 camera interface and advanced audio features with the launch of the SAMA7G54 Arm Cortex A7-based MPU ...

Valens ( ($VLN) ) just unveiled an announcement. On January 5, 2026, Israel-based Valens Semiconductor and Japanese Tier 1 supplier Sakae Riken ...

DCD-SEMI, a provider of silicon-proven IP solutions, announces the availability of the DI3CM-HCI, an advanced MIPI I3C Host Controller Interface (HCI) IP Core designed to modernize peripheral ...

PISCATAWAY, N.J.--(BUSINESS WIRE)--The MIPI Alliance, an international organization that develops interface specifications for mobile and mobile-influenced industries, today announced details of its ...

Streams of data from higher-speed sensors pose throughput and latency challenges for designers. However, optimizing a design for those criteria can come at the expense of increased power consumption ...

It is hard to believe, but it has been 20 years since MIPI Alliance was first founded. The organization was originally formed to standardize the video interface technologies for cameras and displays ...

What is the MIPI DSI-2 protocol? How the MIPI DSI-2 protocol enables very low latency. How the MIPI DSI-2 protocol allows for the implementation of high-performance electronic displays. The MIPI ...

BRIDGEWATER, N.J.--(BUSINESS WIRE)--The MIPI Alliance, an international organization that develops interface specifications for mobile and mobile-influenced industries, today announced a major update ...

The SN65DSI85 DSI to FlatLink bridge features a dual-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating at 1Gbps per lane; a maximum input bandwidth of 8 Gbps. The ...