Advanced CMOS process technologies enable IC designers to deliver higher performing devices, but also increase the need for extra board-level ESD protection to ensure the reliability of the end ...

IC cores have shrunk significantly with ever-smaller process geometries, but the I/Os have basically been stuck at the same sizes since 0.5-micron CMOS. Now with new compact electrostatic discharge ...

New process cuts die size, I/O and ESDNews from E-InSiteSarnoff, the company that pioneered CMOS process technology, has unveiled its TakeCharge! technology for IC design, which it claims reduces die ...

Sofics, a semiconductor integrated circuit IP provider, has announced that its TakeCharge Electrostatic Discharge (ESD) solutions portfolio is now available for TSMC’s advanced 3nm process technology.

Standards for specifying a chip’s ability to withstand electrostatic discharge (ESD) are changing – in some cases, getting tougher, and in others, easing up. ESD protection has been on a path from a ...

Electrostatic discharge (ESD) protection is critical at advanced nodes to safeguard designs against effects intensified by shrinking transistor dimensions and oxide layer thicknesses. On the other ...

BELGIUM – October 21, 2025 – Sofics BV, a world leading solution provider specializing in physical layout and design, with a focus on the built-in robustness of integrated circuits that demand ...

Sofics stands for “Solutions for ICs.” Sofics is an IP provider with a track record in on-chip robustness for ESD, EOS and EMC with an extensive patent portfolio, proven on more than 50 processes. Our ...

This newest offering to Mechnano’s growing portfolio of electrostatic dissipative (ESD) material solutions for Additive Manufacturing (AM) is based on Jabil PK 5000 engineered powder combined with a D ...